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Lead DFT Engineer
Bangalore, India
10+
Full-Time
We are looking for a highly experienced DFT Lead Engineer to take ownership of Design-for-Test (DFT) architecture, implementation, and sign-off for complex flat SoC designs. This role requires deep expertise in PNR (Place-and-Route) within Cadence flow.
Key Responsibilities
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Lead DFT strategy and implementation for flat SoC designs from RTL through tape-out.
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Develop and integrate test architectures including scan insertion, MBIST, LBIST, JTAG, and boundary scan.
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Work closely with the PNR team to ensure DFT structures are timing- and placement-aware.
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Drive test mode constraint creation and ensure compatibility with functional modes.
Qualifications
Must-Have:
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Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering or related field.
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10–12 years of hands-on DFT experience in ASIC/SoC projects.
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Proven PNR experience to handle flat SoC designs in Cadence flow
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Strong knowledge of scan insertion, MBIST, LBIST, boundary scan, JTAG, and related standards (IEEE 1149.x).
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Experience with Synopsys DFT Compiler, Tessent, or equivalent DFT tools.
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Good understanding of STA and SDC constraints for test modes.
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Familiarity with ECO flows in post-PNR stages for DFT fixes.
Nice-to-Have:
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Automotive semiconductor industry experience
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Proficiency in scripting (Tcl, Perl, Python) for automation.
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Low-power DFT experience with UPF/CPF.
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Exposure to signal integrity considerations for test structures.
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Prior technical leadership or mentoring experience.
